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7 / 2 1 v e r . 1 . 0 6 . e l e c t r i c a l sp e c i f i c a t i o n s a n d i n s t r u c t i o n c o d e 6.1 electrical characteristics ite m s y m bol min . t y p . max . u n it suppl y v o ltage ( l ogic) v dd v ss 4 . 75 5 . 0 5 . 25 v suppl y v o ltage (lcd drive) v dd - v o - 1 2 . 0 - v h igh v i h v dd =5.0 0 . 8v dd - v dd +0.3 v input signal v o ltage l o w v i l v dd =5.0 0 - 0 . 2 v dd v suppl y current ( l ogic) i dd - 1. 4 - m a supply current (lcd drive) i ee - 1 . 0 - m a supply current (el) i e l - - 4.8 ma
8/21 ver. 1.0 6.2 interface signals pin no. symbol level description 1 v dd 5.0v supply voltage for logic and lcd(+) 2 v s s 0v g ro un d 3 v ee - operating voltage for lcd (variable) 4 d b 0 h /l da ta b it 0 5 d b 1 h/l data bit1 6 db 2 h/l da ta b it 2 7 d b 3 h/l d a ta bit 3 8 d b 4 h/l d a ta bit 4 9 d b 5 h/l d a ta bit 5 10 d b 6 h/l d a ta bit 6 11 d b 7 h/l d a ta bit 7 12 cs 1 l chip select signal 1 13 cs 2 l chip select signal 2 14 rst l re set signal 15 rw h / l h : r ea d, l:write 16 d /i h / l h : dat a , l : i ns tru ctio n co de 17 e h ,h - > l c hi p e n ab le s ig na l 18 fg 0 v fra me ground 19 el1 - power supply for el backlight 20 el2 - power supply for el backlight
interface ac characteristics mpu interface (gnd = 0v, v cc = 2.7 to 5.5v, ta = ?0 to +75 c) * item symbol min typ max unit note e cycle time t cyc 1000 ns fig. 10, fig. 11 e high level width p weh 450 ns e low level width p wel 450 ns e rise time t r 25 ns e fall time t f 25 ns address setup time t as 140 ns address hold time t ah 10 ns data setup time t dsw 200 ns fig. 10 data delay time t ddr 320 ns fig. 11, fig. 12 data hold time (write) t dhw 10 ns fig. 10 data hold time (read) t dhr 20 ns fig. 11 note: specified at +75 c for die products. viht vilt viht vilt viht vilt t cyc p wel p weh t r t as t as t ah t ah t f viht vilt t dsw t dhw e r/w cs1?s3 d/i db0?b7 figure 9 mpu write timing  * @ $  #2.                                      
t r t cyc p wel p weh t as t as t f t ah t ah viht vilt viht vilt t ddr viht vilt t dhr e r/w cs1?s3 d/i db0?b7 figure 10 mpu read timing                                         
code instructions r/w d/i db7 db6 db5 db4 db3 db2 db1 db0 functions display on/off 0000111111/0 controls display on/off. ram data and internal status are not affected. 1: on, 0: off. display start line 0011 display start line (0?3) specifies the ram line displayed at the top of the screen. set page (x address) 0010111p age (0?) sets the page (x address) of ram at the page (x address) register. set y address 0001y address (0?3) sets the y address in the y address counter. status read 1 0 busy 0 on/ reset 0000 reads the status. off reset 1: reset 0: normal on/off 1: display off 0: display on busy 1: internal operation 0: ready write display data 0 1 w rite data writes data db0 (lsb) has access to the to db7 (msb) on the address of the display data bus into display ram specified in ram. advance. after the read display data 1 1 read data reads data db0 (lsb) access, y address is to db7 (msb) from the increased by 1. display ram to the data bus. note: busy time varies with the frequency (f clk ) of ?, and ?. (1/f clk t busy 3/f clk )  *'@  2                                           
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